1. Field of the Invention
The present invention relates to a semiconductor memory which has a bit width control function of input/output (I/O) data.
2. Description of the Related Art
With the development of a minute processing technique, the capacity and operation speed of a semiconductor memory has increased. User's requests for product have diversified. In order to increase the capacity, a decrease in bit width of address data and an increase in bit width of I/O data are required. In order to increase operation speed, serial input and output functions in synchronization with a high-speed clock, i.e., burst mode, is required. It is possible to improve the number of bits of I/O data per time by use of the burst mode.
With respect to a semiconductor memory having wide bit width, it is desirable to vary the bit width of the I/O data. A semiconductor memory having a bit width control function of the output data includes a memory core, a plurality of multiplexers connected to the memory core, and a plurality of shift registers connected to the multiplexers. Each multiplexer selects read-data from the memory core for read out. The output data of multiplexer is subjected to parallel-serial (P/S) convert by the shift registers.
However, since the memory core takes up most of the area on the semiconductor chip, the length of the longest wire between the memory core and the multiplexers is about ¼ of the length of the long side of the semiconductor chip. The wiring resistance caused by each input of the multiplexers creates a large delay. As a result, dispersion of wiring delay occurs in the wiring between the memory core and the multiplexers. In order to reduce such delay, it is necessary to increase the width of each wiring by use of upper wiring layer. Therefore, when the bit width control function of the I/O data is added to a semiconductor memory capable of transmitting and receiving the data at high speed, the chip size of the semiconductor memory increases.